1. Field of the Invention
This invention relates to a method for automatic generation of LSI layout patterns, print substrates, and the like and more specifically concerns a method for determining the absence of errors, and implementation of changes in the layout patterns generated with reference to the design rules.
2. Description of the Prior Art
In conventional LSI patterns formed by automatic layout systems, i.e. CAD systems, it is difficult to remove the notches (depressions with widths smaller than a minimum spacing) and slits (grooves with widths smaller than a minimum spacing) formed on the patterns with the same potential. One approach is to ignore them on the assumption that they pose no hazard to the electrical performance. Another approach is to perform an OR operation on the pattern. The obtained polygonal pattern is then geometrically processed.
Ignoring the notches and slits presents problems. The notches and slits cause many pseudo-errors to be generated by the design rule check system, making detection of the intrinsic fatal errors difficult. The notches and slits may also hamper the correct formation of the patterns in the LSI fabrication process.
Using the OR operation approach also presents problems. When geometric processing is performed for a polygonal pattern, not only is processing complicated, but an OR operation of the pattern must be performed in advance.
Several studies have been reported in symposia concerning schemes for identification of the connectivity of patterns, such as N. Miyahara et al.: Proc. ISCAS Conf., pp. 114-117, 1981. However, the methods discussed, utilize the input data in polygonal form with only layer properties. The result is rather complicated processing.